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2141d?hirel?02/04 features 22.8 specint95 (estimated), 17specfp95 at 500 mhz (estimated) 917mips at 500 mhz selectable bus clock (14 cpu bus dividers up to 9x) seven selectable core-to-l2 frequency divisors selectable 603 interface voltage below 3.3v (1.8v, 2.5v) selectable l2 interface of 1.8v or 2.5v p d typical 5.3w at 500 mhz, full operating conditions nap, doze and sleep modes for power saving superscalar (four instructions fetched per clock cycle) 4 gb direct addressing range virtual memory: 4 hexabytes (2 52 ) 64-bit data and 32-bit address bus interface 32 kb instruction and data cache eight independent execution units and three register files write-back and write-through operations f int max = 450 mhz 500 mhz f bus max = 133 mhz description the PC7410 is the second microprocessor that uses the fourth (g4) full implementa- tion of the powerpc ? reduced instruction set computer (risc) architecture. it is fully jtag-compliant. the PC7410 maintains some of the characteristics of g3 microprocessors: the design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units the microprocessor provides four software controllable power-saving modes and a thermal assist unit management the microprocessor has separate 32-kbyte, physically-addressed instruction and data caches with dedicated l2 cache interface with on-chip l2 tags in addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency protocol (4 mesi states plus a fifth state for shared intervention) and an implementation of the new altivec ? technology instruc- tion set. new features have been developed to make latency equal for double-precision and single-precision floating-point operations in volving multiplication. additionally, in mem- ory subsystem (mss) bandwidth, the PC7410 offers an optional, high-bandwidth mpx bus interface. unlike the pc7400, the PC7410 does not support the 3.3v i/o on the l2 cache interface. powerpc 7410 risc microprocessor product specification PC7410 rev. 2141d?hirel?02/04
2 PC7410 2141d?hirel?02/04 screening cbga upscreenings based on atmel standards full military temperature range (t j = -55 c, +125 c), industrial temperature range (t j = -40 c, +110 c) ci-cga package version, hitce package version g suffix cbga 360 ceramic ball grid array gh suffix hitce 360 ceramic ball grid array cicga 360 ceramic ball grid array with solder column interposer (sci) gs suffix
3 PC7410 2141d?hirel?02/04 block diagram figure 1. PC7410 microprocesso r block diagram f etcher branch processing unit instruction queue 6-word dispatch unit instruction unit data mmu srs (original) 128-entry dtlb dbat arra y instr uction mmu srs (shadow) 128-entry itlb ibat arra y reservation station vector permute unit vector alu integer unit 1 integer unit 2 system register unit reservation station reservation station reservation station reservation station reservation station 2-entr y reservation station vr file 6 rename buffers gpr file 6 rename buffers fpr file 6 rename buff ers load/store unit floating point unit completion unit 8-entry reorder buffer vsiu vciu vfpu tags 32-kbyte icache tags 32-kbyte dcache 64-entry btic/512-entry bht lr/ctr add-multiply- divide - add - vscr - add - add-multiply- divide fpscr ea calculation finished stores completed stores 128-bit 32-bit 128-bit 2 instructions 32-bit 64-bit (2 instructions) 32-bit address bus 64- or 32-bit l2 data bus 19-bit l2 address bus 64-bit data bus 32-bit ea pa 64-bit 64-bit data reload buffer data reload table instruction reload buffer instruction reload table memory subsystem l2 miss data transaction queue l2 castout bus interface unit l2 data transaction queue l2 controller l2 tags l2cr l2pmcr additional features time base counter/decrementer clock multiplier jtag/cop interface thermal/power management performance monitor 128 bits 128 bits (4 instructions)
4 PC7410 2141d?hirel?02/04 general parameters table 1 provides a summary of the general parameters of the PC7410. note: 1. 3.3v i/o bus not supported for 1.5v core power supply processor version. features this section summarizes features of the PC7410?s implementation of the powerpc architecture. major features of the PC7410 are as follows: branch processing unit ? four instructions fetched per clock ? one branch processed per cycle (plus resolving two speculations) ? up to one speculative stream in execution, one additional speculative stream in fetch ? 512-entry branch history table (bht) for dynamic prediction ? 64-entry, 4-way set associative branch target instruction cache (btic) for eliminating branch delay slots dispatch unit ? full hardware detection of dependencies (resolved in the execution units) ? dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, altivec permute, altivec alu) ? serialization control (predispatch, postdispatch, execution serialization) decode ? register file access ? forwarding control ? partial instruction decode completion ? 8-entry completion buffer ? instruction tracking and peak completion of two instructions per cycle table 1. device parameters parameter description technology 0.18 m cmos, six-layer metal die size 6.32 mm 8.26 mm (52 mm 2 ) transistor count 10.5 million logic design fully-static packages surface-mount 360 ceramic ball grid array (cbga) surface mount 360 high coefficient of thermal expansion ceramic ball grid array (hitce) surface mount 360-column ci-cga package core power supply 1.8v 100 mv dc or 1.5v 50 mv dc (nominal; see table 4 for recommended operating conditions) i/o power supply 1.8v 100 mv dc or 2.5v 100 mv 3.3v 165 mv (603 bus only) (1) (input thresholds are configuration pin selectable) or
5 PC7410 2141d?hirel?02/04 ? completion of instructions in program order while supporting out-of-order instruction execution, completion se rialization and all instruction flow changes fixed-point units (fxus) that share 32 gprs for integer operands ? fixed-point unit 1 (fxu1)?multiply, divide, shift, rotate, arithmetic, logical ? fixed-point unit 2 (fxu2)?shift, rotate, arithmetic, logical ? single-cycle arithmetic, shifts, rotates, logical ? multiply and divide support (multi-cycle) ? early out multiply three-stage floating-point unit and a 32-entry fpr file ? support for ieee-754 standard single- and double-precision floating-point arithmetic ? three-cycle latency, one-cycle thro ughput (single or double precision) ? hardware support for divide ? hardware support for denormalized numbers ? time deterministic non-ieee mode system unit ? executes cr logical instructions an d miscellaneous system instructions ? special register transfer instructions altivec unit ? full 128-bit data paths ? two dispatchable units: vector permute unit and vector alu unit ? contains its own 32-entry 128-bit vector register file (vrf) with six renames ? the vector alu unit is further sub-divided into the vector simple integer unit (vsiu), the vector complex integer unit (vciu) and the vector floating-point unit (vfpu). ? fully pipelined load/store unit ? one-cycle load or store cache access (byte, half-word, word, double-word) ? two-cycle load laten cy with one-cycle throughput ? effective address generation ? hits under misses (multiple outstanding misses) ? single-cycle unaligned access within double-word boundary ? alignment, zero padding, sign extend for integer register file ? floating-point internal format conversion (alignment, normalization) ? sequencing for load/store multiples and string operations ? store gathering ? executes the cache and tlb instructions ? big- and little-endian byte addressing supported ? misaligned little-endian supported ? supports fxu, fpu, and altivec load/store traffic ? complete support for all four architecture altivec dst streams level 1 (l1) cache structure ? 32k 32-byte line, 8-way set associative instruction cache (il1)
6 PC7410 2141d?hirel?02/04 ? 32k 32-byte line, 8-way set associative data cache (dl1) ? single-cycle cache access ? pseudo least-recently-used (lru) replacement ? data cache supports altivec lru and transient instructions algorithm ? copy-back or write-through data cache (on a page-per-page basis) ? supports all powerpc memory coherency modes ? non-blocking instruction and data cache ? separate copy of data cache tags for efficient snooping ? no snooping of instruction cache except for icbi instruction level 2 (l2) cache interface ? internal l2 cache controller and tags; external data srams ? 512k, 1m and 2-mbyte 2-way set associative l2 cache support ? copyback or write-through data cache (on a page basis or for all l2) ? 32-byte (512k), 64-byte (1m), or 128-byte (2m) sectored line size ? supports pipelined (register-regi ster) synchronous burst srams and pipelined (register-register) late-write synchronous burst srams ? supports direct mapped mode for 256k, 512k, 1m or 2 mbytes of sram (either all, half or none of l2 sram must be configured as direct mapped. ? core-to-l2 frequency divisors of 1, 1.5, 2, 2.5, 3, 3.5, and 4 supported ? 64-bit data bus which also support 32-bits bus mode ? selectable interface voltages of 1.8v and 2.5v memory management unit ? 128 entry, 2-way set associative instruction tlb ? 128 entry, 2-way set associative data tlb ? hardware reload for tlbs ? four instruction bats and four data bats ? virtual memory support for up to four petabytes (2 52 ) of virtual memory ? real memory support for up to four gigabytes (2 32 ) of physical memory ? snooped and invalidated for tlbi instructions efficient data flow ? all data buses between vrf, load/store unit, dl1, il1, l2 and the bus are 128 bits wide ? dl1 is fully pipelined to provide 128 bits per cycle to/from the vrf ? l2 is fully pipelined to provide 128 bits per l2 clock cycle to the l1s ? up to eight outstanding out-of-order cache misses between dl1 and l2/bus ? up to seven outstanding out-of-order transactions on the bus ? load folding to fold new dl1 misses into older outstanding load and store misses to the same line ? store miss merging for multiple st ore misses to the same line. only coherency action taken (i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed). ? two-entry finished store queue and four-entry completed store queue between load/store unit and dl1
7 PC7410 2141d?hirel?02/04 ? separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dl1 and l2 bus interface ? mpx bus extension to 60x processor interface ? mode-compatible with 60x processor interface ? 32-bit address bus ? 64-bit data bus ? bus-to-core frequency multipliers of 2x , 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported ? selectable interface voltages of 1.8v, 2.5v and 3.3v power management ? low-power design with thermal requirements very similar to pc740 and pc750 ? low voltage 1.8v or 1.5v processor core ? selectable interface voltages of 1.8v can reduce power in output buffers ? three static power saving modes: doze, nap, and sleep ? dynamic power management testability ? lssd scan design ? ieee 1149.1 jtag interface ? array built-in self test (abist) ? factory test only ? redundancy on l1 data arrays and l2 tag arrays reliability and serviceability ? parity checking on 60x and l2 cache buses
8 PC7410 2141d?hirel?02/04 signal description figure 2. PC7410 microprocessor signal groups pcx7410 v dd ov dd av dd l2ov dd l2av dd 13 49 1 gnd ts chk gbl artry wt ci dbg d[0:63] dp[0:7] ta dti1 tea br bg abb/amon[0] a[0:31] ap[0:3] tt[0:4] tbst tsiz[0:2] aack dbwo, dti(0) dbb, dmon(0) dti(2) l2ce l2we sreset hreset hit l2addr[0:18] l2data[0:63] l2dp[0:7] l2clkouta, l2clkoutb l2sync_out l2sync_in l2zz int smi mcp ckstp_in ckstp_out shdo, shd1 rsrv 1 1 1 1 32 4 5 1 3 1 1 1 1 1 1 1 1 1 64 8 1 1 1 1 19 64 8 1 1 1 2 1 1 1 1 1 1 1 1 1 1 tben emode qreq qack drdy sysclk pll_cfg[0:3] clk_out jtag:cop factory test l1_tstclk, l2_tstclk bvsel l2vsel 1 2 1 1 1 1 1 1 1 4 1 5 3 1 1 12 20 1 l2 cache address/data address arbitration address bus address start transfer attribute address termination data arbitration data transfer data termination l2 cache clock/control interrupts reset processor status control clock control test interface lssd_mode i/o voltage selection
9 PC7410 2141d?hirel?02/04 detailed specification scope this drawing describes the specific r equirements for the microprocessor PC7410 in compliance with atmel-grenoble standard screening. applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535: appendix a: genera l specifications for microcircuits requirements general the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections depending on the package, the terminal connections are as shown in table 16, table 4 and figure 2. absolute maximum ratings notes: 1. functional and tested operating conditions are given in table 4. absolute maximum ratings are stress ratings only. stre sses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: v in must not exceed ov dd or l2ov dd by more than 0.2v at any time including during power-on reset. 3. caution: l2ov dd /ov dd must not exceed v dd /av dd /l2av dd by more than 2.0v at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. caution: v dd /av dd /l2av dd must not exceed l2ov dd /ov dd by more than 0.4v at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. v in may overshoot/undershoot to a voltage and for a maximum duration as shown in figure 3. 6. PC7410rxnnnle (rev 1.4) and later only. previous revisions do not support 3.3v ov dd and have a maximum value ov dd of -0.3 to 2.6v. table 2. absolute maximum ratings (1) symbol characteri stic value unit v dd core supply voltage -0.3 to 2.1 (4) v av dd pll supply voltage -0.3 to 2.1 (4) v l2av dd l2 dll supply voltage -0.3 to 2.1 (4) v ov dd 60x bus supply voltage -0.3 to 3.465 (3)(6) v l2ov dd l2 bus supply voltage -0.3 to 2.6 (3) v v in processor bus input voltage -0.3 to ovdd + 0,2v (2)(5) v v in l2 bus input voltage -0.3 to l2ovdd + 0,2v (2)(5) v v in jtag signal input voltage -0.3 to ovdd + 0,2v v t stg storage temperature range -55 to 150 c rework temperature 260 c
10 PC7410 2141d?hirel?02/04 figure 3. overshoot/undershoot voltage the PC7410 provides several i/o voltages to support both compatibility with existing systems and migration to future systems. the PC7410 ?core? voltage must always be provided at nominal voltage (see table 4 for actual recommended core voltage). volt- age to the l2 i/os and processor interface i/os are provided through separate sets of supply pins and may be provided at the voltages shown in table 3. the input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal hreset . the output voltage will swin g from gnd to the maxi- mum voltage applied to the o v dd or l2o v dd power pins. notes: 1. caution: the input threshold selection must agree with the ov dd /l2ov dd voltages supplied. 2. to select the 2.5v thre shold option, l2vsel/bvsel should be tied to hreset so that the two signals change state together. this is the preferred method for selecting this mode operation. 3. to overcome the internal pull-up resistance, a pull-down resistance less than 250 ? should be used. 4. default voltage setting if left unconnected (internal pulled-up). parts rev 1.4 and later only. previous revisions do not support 3.3v ov dd , the default voltage setting if left unconnected is 2.5v. 5. parts rev 1.4 and later only. previous revisions do not support 3.3v ov dd , having bvsel = 1 selects the 2.5v threshold. 6. parts rev 1.4 and later only. previous revisions do not support bvsel = hreset. 7. nspec does not support the default ov dd setting of 3.3v. the bvsel input must be tie either low or hreset . table 3. input threshold voltage setting bvsel signal processor bus input threshold is relative to: l2vsel signal (3) l2 bus input threshold is relative to: 0 (1) 1.8v 0 1.8 hreset (1)(2) 2.5v hreset 2.5 1 (1)(4)(5) 3.3v (7) 12.5 hreset (6) 3.3v (7) hreset not supported not to exceed 10% of t sysclk (l2)ov dd + 20% (l2)ov dd + 5% (l2)ov dd v ih v il gnd gnd - 0.3v gnd - 0.7v
11 PC7410 2141d?hirel?02/04 recommended operating conditions notes: 1. these are the recommended and tested operating condition s. proper device operation outside of these conditions is not guaranteed. 2. PC7410rxnnnle (rev 1.4) and later only. previous revisions do not support 3.3v ov dd and have a recommended ov dd value of 2.5v 100 mv for bvsel = 1. 3. PC7410rxnnnle (rev 1.4) and later only. previous revisions do not support bvsel = hreset. 4. not supported for n spec with v dd = 1.5v table 4. recommended operating conditions (1) symbol characteristic recommended value unit v dd core supply voltage 1.8 100 mv or 1.5 50 mv v av dd pll supply voltage 1.8 100 mv or 1.5 50 mv v l2av dd l2 dll supply voltage 1.8 100 mv or 1.5 50 mv v ov dd processor bus supply voltage see note (3) bvsel = 0 1.8 100 mv v ov dd bvsel = hreset 2.5 100 mv v ov dd (2)(3) bvsel = 1 or = hreset (4) 3.3 165 mv v l2ov dd l2 bus supply voltage l2vsel = 0 1.8 100 mv v l2ov dd l2vsel = 1 (2) or l2vsel = hreset 2.5 100 mv v v in input voltage processor bus gnd to ov dd v v in l2 bus gnd to l2ov dd v v in jtag signals gnd to ov dd v t j die-junction temperature -55 to 125 c
12 PC7410 2141d?hirel?02/04 thermal characteristics package characteristics notes: 1. junction temperature is a function of on-chip power diss ipation, package thermal resistance, mounting site (board) temp era- ture, ambient temperature, air flow, power dissipation of ot her components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 wit h the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. boar d temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surf ace as measured by the cold plate method (mil spec-883 method 1012.1) with the calculated case temperature. the actual value of r jc for the part is less than 0.1c/w. see ?thermal management information? on page 13 for more details about thermal management. the board designer can choose between several commercially available heat sink types to place on the PC7410. for exposed-die packaging technology as in table 5, the intrinsi c conduction thermal resistance paths are shown in figure 4. package thermal characteristics for hitce table 6 provides the package thermal characteristics for the PC7410, hitce. notes: 1. simulation, no convection air flow. 2. per jedec jesd51-6 with the board horizontal. package thermal characteristics for ci-cga table 5. package thermal characteristics cbga symbol characteristic value PC7410 cbga unit r ja junction-to-ambient thermal resistance, nat ural convection, single-layer (1s) board (1)(2) 24 c/w r jma junction-to-ambient thermal resistance, nat ural convection, four-layer (2s2p) board (1)(3) 17 c/w r jma junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board (1)(3) 18 c/w r jma junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board 16 c/w r jma junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board (1)(3) 14 c/w r jma junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board 13 c/w r jb junction-to-board thermal resistance (4) 8 c/w r jc junction-to-case thermal resistance (5) < 0.1 c/w table 6. package thermal characte ristics for hitce package characteristic symbol value unit PC7410 hitce junction-to-bottom of balls (1) r j 6.8 c/w junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board (1)(2) r jma 20.7 c/w junction to board thermal resistance r jb 11.0 c/w table 7. package thermal characteristics for ci-cga characteristic symbol value unit PC7410 ci-cga junction to board thermal resistance r jb 8.42 c/w
13 PC7410 2141d?hirel?02/04 internal package conduction resistance figure 4 depicts the primary heat transfer path for a package with an attached heat sink mounted on a printed circuit board. heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material) and finally to the heat sink where it is removed by forced-air convection. since the silicon thermal resistan ce is quite small, for a fi rst-order analysi s the tempera- ture drop in the silicon may be neglected. thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. figure 4. c4 package with heat sink mounted on a printed circuit board thermal management information this section provides thermal management information for the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design ? the heat sink, airflow and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package and mounting clip and screw assembly; see figure 5. this spring force should not exceed 5.5 pounds of force. ultimately, the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly and cost. figure 5. cbga package cross-section with heat sink options external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed circuit board radiation convection printed-circuit board adhesive or thermal interface material heat sink clip heat sink option
14 PC7410 2141d?hirel?02/04 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 6 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of contact pressure. as shown, the perfor- mance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed- circuit board (see figure 5). this spring force should not exceed 5.5 pounds of force. therefore, synthetic grease offers the best thermal performance, considering the low interface pressure. the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected base d upon high conductivity, yet must have adequate mechanical strength to meet equipment shock/vibration requirements. figure 6. thermal performance of different thermal interface materials 0 0.5 1 1.5 2 010 203040506070 80 silicone sheet (0.006") bare joint floroether oil sheet (0.007") graphite/oil sheet (0.005") synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
15 PC7410 2141d?hirel?02/04 heat sink selection example for preliminary heat sink sizing, the di e-junction temperature can be expressed as follows: where: t j = die-junction temperature t a = inlet cabinet ambient temperature t r = air temperature rise within the computer cabinet jc = junction-to-case thermal resistance int = adhesive or interface material thermal resistance sa = heat sink base-to-ambient thermal resistance p d = power dissipated by the device during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 4. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 c to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 c to 10 c. the thermal resistance of the thermal interface material ( int ) is typically about 1 c/w. assuming a t a of 30 c, a t r of 5 c, a cbga package jc = 0.03, and a power consumption (p d ) of 5.0 watts, the following expression for t j is obtained: for a thermally heat sink #2328b, the heat sink-to-ambient thermal resistance ( sa ) ver- sus airflow velocity is shown in figure 7. t j t a t r jc int sa ++ () p d ++ = t j 30 c 5 c 0,03 cw ? 1,0 cw ? sa ++ () 5 w ++ =
16 PC7410 2141d?hirel?02/04 figure 7. thermalloy #2328b heat sink-to-ambient thermal resistance vs. airflow velocity assuming an air velocity of 0.5 m/s, the effective r sa is 7 c/w, thus , resulting in a die-junction temperature of approximately 75 c which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, wakefield engineering and aavid engineering offer different heat si nk-to-ambient thermal resistances and may or may not need air flow. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging te chnologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can ade- quately describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of the component-level thermal resistance, but of the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature ? airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. 1 3 5 7 8 00.511.522.53 3.5 thermalloy #2328b pin-fin heat sink (25 x 28 x 15 mm) approach air velocity (m/s) heat sink thermal resistance (c/w) 2 4 6 t j 30 c 5 c 0,03 cw ? 1,0 cw ? 7 cw ? ++ () 5 w ++ =
17 PC7410 2141d?hirel?02/04 due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection and conduction) may vary widely. for these reasons, it is recommended to use conjugate heat transfer models for the board, as well as system- level designs. to expedite system-level thermal analysis, several ?compact? thermal-package models are available within flotherm ? . these are available upon request. power consideration power management the PC7410 provides four power modes, se lectable by setting the appropriate control bits in the msr and hido registers. the four power modes are: full-power: this is the default power state of the PC7410. the PC7410 is fully powered and the internal functional units are operating at the full processor clock speed. if the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution or external hardware. doze: all the functional units of the PC7410 are disabled except for the time base/decrementer registers and the bus snooping logic. when the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine check brings the PC7410 into the full-power state. the PC7410 in doze mode maintains the pll in a fully powered state and locked to the system external clock input (sysclk) so a transition to the full-power state takes only a few processor clock cycles. nap: the nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the pll in a powered state. the PC7410 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (mcp ). a return to full-power state from a nap state takes only a few processor clock cycles. when the processor is in nap mode, if qack is negated, the processor is put in doze mode to support snooping. sleep: sleep mode minimizes power consumption by disabling all internal functional units, after which exte rnal system logic may disable the pll and sysclk. returning the PC7410 to the full-power state requires the enabling of the pll and sysclk, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check input (mcp ) signal after the time required to relock the pll.
18 PC7410 2141d?hirel?02/04 power dissipation notes: 1. these values apply for all valid processor bus and l2 bus ratios. the values do not include i/o supply power (ov dd and l2ov dd ) or pll/dll supply power (av dd and l2av dd ). ov dd and l2ov dd power is system dependent, but is typically <10% of v dd power. worst case power consumption for av dd = 15 mw and l2av dd = 15 mw. 2. maximum power is measured at 105c, at v dd = 1.8v or 1.5vwhile running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including altivec, maximally busy. 3. typical power is an average value measured at 65c, v dd = 1.8v or 1.5v, ov dd = l2ov dd = 2.5v in a system while running a codec application that is altivec intensive. 4. these values include the use of altivec. without altivec operation, estimate a 25% decrease. 5. power consumption derating at low te mperatures to be defined after device characterization. table 8. power consumption for PC7410 (1.8v) processor (cpu) frequency unit power mode 400 mhz 450 mhz 500 mhz core power supply 1.5v 1.8v 1.5v 1.8v 1.8 v full-on mode typical (1)(3) 2.92 4.2 3.29 4.7 5.3 w maximum (1)(2)(4)(5) 6.6 9.5 7.43 10.7 11.9 w doze mode maximum (1)(2)(5) 3.6 4.3 4.1 4.8 5.3 w nap mode maximum (1)(2)(5) 1.35 1.35 1.5 1.5 1.65 w sleep mode maximum (1)(2)(5) 1.3 1.3 1.45 1.45 1.6 w sleep mode - pll and dll disabled typical (1)(3) 600 600 600 600 600 mw maximum (1)(2)(5) 1.1 1.1 1.1 1.1 1.1 w
19 PC7410 2141d?hirel?02/04 electrical characteristics static characteristics notes: 1. nominal voltages; see table 4 for recommended operating conditions. 2. for processor bus signals, the reference is ov dd while l2ov dd is the reference for the l2 bus signals. 3. excludes factory test signals. 4. capacitance is periodically sampled rather than 100% tested. 5. the leakage is measured for nominal ov dd and l2ov dd , or both ov dd and l2ov dd must vary in the same direction (for example, both ov dd and l2ov dd vary by either +5% or ?5%). 6. measured at max ov dd /l2ov dd 7. excludes ieee 1149.1 boun dary scan (jtag) signals. table 9. dc electrical specifications (see table 4 for recommended operating conditions ) symbol characteristic nominal bus voltage (1) min max unit v ih input high voltage (all inputs except sysclk) (2)(3)(8) 1.8 0.65 x (l2)ov dd (l2)ov dd + 0.2 v v ih 2.5 1.7 (l2)ov dd + 0.2 v ih 3.3 2.0 ov dd + 0.3 v il input low voltage (all inputs except sysclk) (8) 1.8 -0.3 0.35 x (l2)ov dd v v il 2.5 -0.3 0.2 x (l2)ov dd v il 3.3 -0.3 0.8 cv ih sysclk input high voltage (2)(8) 1.8 1.5 ov dd + 0.2 v cv ih 2.5 2.0 ov dd + 0.2 cv ih 3.3 2.4 ov dd + 0.3 cv il sysclk input low voltage (8) 1.8 -0.3 0.2 v cv il 2.5 -0.3 0.4 cv il 3.3 -0.3 0.4 i in input leakage current, v in = l2ov dd /ov dd (2)(3)(6)(7) 1.8 ? 20 a i in 2.5 ? 35 i in 3.3 ? 70 i tsi high-z (off-state) leakage current, v in = l2ov dd /ov dd (2)(3)(5)(7) 1.8 ? 20 a i tsi 2.5 ? 35 i tsi 3.3 ? 70 v oh output high voltage, i oh = -6 ma (8) 1.8 (l2)ov dd - 0.45 ? v v oh 2.5 1.7 ? v oh 3.3 2.4 ? v ol output low voltage, i ol = 6 ma (8) 1.8 ? 0.45 v v ol 2.5 ? 0.4 v ol 3.3 ? 0.4 c in capacitance, v in = 0v, f = 1 mhz (3)(4)(7) ?6.0pf
20 PC7410 2141d?hirel?02/04 8. for jtag support: all signals controlled by bvsel and l2vsel will see v il /v ih /v ol /v oh /cv ih /cv il dc limits of 1.8v mode while either the extest or clamp instruct ion is loaded into the ieee 1149.1 instruction register by the updateir tap state until a different instruction is loaded into the instruction regist er by either another updateir or a test-logic-reset tap stat e. if only tsrt is asserted to the part, and then a sample instruction is executed, there is no way to control or predict what the dc voltage limit s are. if hreset is asserted before executing a sample instruction, the dc voltage limits will be con- trolled by the bvsel/l2vsel settings during hreset . anytime hreset is not asserted (i.e., just asserting trst ) , the voltage mode is not known until either extes t or clamp is executed, at which time the voltage level will be at the dc limits of 1.8v. dynamic characteristics after fabrication, parts are sorted by maximum processor core frequency as shown in ?clock ac specifications? and tested for conformance to the ac specifications for that frequency. these specifications are for valid processor core frequencies. the processor core frequency is determined by the bus ( sysclk) frequency and the settings of the pll_cfg[0:3] signals. parts are sold by maximum processor core frequency. clock ac specifications table 10 provides the clock ac timing sp ecifications as defined in figure 8. notes: 1. caution: the sysclk fr equency and pll_cfg[0:3] settings must be chosen such th at the resulting sysclk (bus) fre- quency, cpu (core) frequency and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:3] signal description in ?clock selection? on page 39 for valid pll_cfg[0:3] settings 2. rise and fall times for the sysclk input measured from 0.4v to 2.4v when ov dd = 3.3v nominal. 3. rise and fall times for the sysclk input measured from 0.2v to 1.2v when ov dd = 1.8v or 2.5v nominal. 4. timing is guaranteed by design and characterization. 5. this represents total input jitt er, short-term and long-term combined, and is guaranteed by design. 6. relock timing is guaranteed by design and characterization. pl l-relock time is the maximum amount of time required for pll lock after a stable v dd and sysclk are reached during the power-on rese t sequence. this specification also applies when the pll has been disabled and subsequently re-enabl ed during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. table 10. clock ac timing specifications (see ta ble 4 for recommended operating conditions ) symbol characteristic maximum processor core frequency unit 400 mhz 450 mhz 500 mhz min max min max min max f core (1) processor frequency 350 400 350 450 350 500 mhz f vco (1) vco frequency 700 800 700 900 700 1000 mhz f sysclk (1) sysclk frequency 33 133 33 133 33 133 mhz t sysclk sysclk cycle time 7.5 30 7.5 30 7.5 30 ns t kr & t kf (2) sysclk rise and fall time 1.0 1.0 1 ns t kr & t kf (3) 0.5 0.5 0.5 ns t khkl /t sysclk (4) sysclk duty cycle measured at ov dd /2 40 60 40 60 40 60 % sysclk jitter (5) 150 150 150 ps internal pll relock time (6) 100 100 100 s
21 PC7410 2141d?hirel?02/04 figure 8. sysclk input timing diagram note: vm = midpoint voltage (ov dd /2) processor bus ac specifications table 11 provides the processor ac timing specifications for the PC7410 as defined in figure 10 and figure 11. timing specifications for the l2 bus are provided in ?l2 bus ac specifications? on page 26. notes: 1. all input specifications are measur ed from the midpoint of the signal in question to the midpoint of the rising edge of the input sysclk. all output specifications are measured from the midpoi nt of the rising edge of sysclk to the midpoint of the sig- nal in question. all output timings assume a purely resistive 50 ? load (see figure 10). input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. the symbology used for timing specific ations herein follows the pattern of t (signal)(state)(reference)(state) for inputs and t (reference)(state)(signal)(state) for outputs. for example, t ivkh symbolizes the time input signals (i) reach the valid state (v) relative to the sysclk reference (k) going to the high (h) state or input setup time. and t khov symbolizes the time from sysclk (k) going hi gh (h) until outputs (o) are valid (v) or output valid time. i nput hold time can be read as the time that the input signal (i) went invalid (x) wi th respect to the rising clock edge (kh) - note the position o f the reference and its state for inputs -and output hold time can be read as the time from the rising edge (kh) until the output went invalid (ox). 3. the setup and hold time is with re spect to the rising edge of hreset (see figure 11). 4. this specification is for configuration mode select only. also note that the hreset must be held asserted for a minimum of 255 bus clocks after the pll re-lock time during the power-on reset sequence. 5. t sysclk is the period of the external clock (sysclk) in nanoseconds(ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time durati on (in nanoseconds) of t he parameter in question. 6. mode select signals are bvsel, emode, l2vsel, pll_cfg[0:3] sysclk vm vm vm cvil cvih t khkl t sysclk t kr t kf table 11. processor bus ac timing specifications (1) at v dd = av dd = 1.8v 100 mv; -55c t j 125c, ov dd = 1.8v 100 mv symbol (2) parameter 400, 450, 500 mhz unit min max t ivkh input setup 1.0 ? ns t ixkh input hold 0?ns t khtsv t kharv t khov output valid times: (7)(8) ts artry /shd0 /shd1 all other outputs ? ? ? 3.0 2.3 3.0 ns t khtsx t kharx t khox output hold times: (7)(12) ts artry /shd0 /shd1 all other outputs 0.5 0.5 0.5 ? ? ? ns t khoe (11) sysclk to output enable 0.5 ? ns t khoz sysclk to output high imped ance (all except abb/amon [0], artry /shd , dbb /dmon [0]), shd0 , shd1 ) ?3.5ns t khabpz (5)(9)(11) sysclk to abb /amon [0], dbb /dmon [0] high impedance after precharge ? 1 t sysclk t kharp (5)(10)(11) maximum delay to artry /shd0 /shd1 precharge ? 1 t sysclk
22 PC7410 2141d?hirel?02/04 7. all other output signals are composed of th e following - a[0:31], ap[0:3], tt[0:4], tbst , tsiz[0:2], gbl , wt , ci, dh[0:31], dl[0:31], dp[0:7], br , ckstp_out , drdy , hit , qreq , rsrv . 8. output valid time is measured from 2.4v to 0.8v which may be longer than the time required to discharge from vdd to 0.8v. 9. according to the 60x bus protocol, abb and dbb are driven only by the currently acti ve bus master. they are asserted low then precharged high before returning to high-z as sh own in figure 9. the nominal precharge width for abb or dbb is 0.5 x t sysclk , i.e., less than the minimum t sysclk period, to ensure that a nother master asserting abb , or dbb on the following clock will not contend with the precharge. output valid and output hold timing is tested for the signal asserted. output valid time is tested for precharge.the high-z behavior is guaranteed by design. 10. according to the 60x bus protocol, artry can be driven by multiple bus masters through the clock period immediately fol- lowing aack . bus contention is not an issue since any master asserting artry will be driving it low. any master asserting it low in the first clock following aack will then go to high-z for one clock before precha rging it high dur ing the second cycle after the assertion of aack . the nominal precharge width for artry is 1.0 t sysclk ; i.e., it should be high-z as shown in fig- ure 9 before the first opportunity for another master to assert artry . output valid and output hold timing are tested for the signal asserted. output valid time is tested for prec harge. the high-z behavior is guaranteed by design. 11. guaranteed by design and not tested. 12. output hold time characteristics can be altered by the use of the l2_tstck pi n during system reset, si milar to l2 output hold being altered by the use of bits [14-15] in the l2cr r egister. information on the operation of the l2_tstclk will be included in future revisions of this specification. figure 9. input/output timing diagram t ivkh t ixkh t khov t khox t khoe t khoz t khtsv t khtsv t khabpz t khtsx t kharv t kharv t kharpz t kharp t kharx vm = midpont voltage (ov dd /2) sysclk all inputs vm vm vm all outputs (except ts, abb, artry, dbb) ts, abb/amon[0], dbb/dmon[0] all outputs (except ts, abb, artry, dbb) artry, shd0, shd1
23 PC7410 2141d?hirel?02/04 figure 10. ac test load for the 60x interface figure 11 provides the mode select input timing diagram for the PC7410. the mode select inputs are sampled twice, once before and once after hreset negation. figure 11. mode input timing diagram where vm = midpoint voltage (ov dd /2) l2 clock ac specifications the l2clk frequency is programmed by the l2 configuration register (l2cr[4:6]) core- to-l2 divisor ratio. see table 18 for example core and l2 frequencies at various divi- sors. table 12 provides the potential range of l2clk output ac timing specifications as defined in figure 12. the l2sync_out signal is intended to be routed halfway out to the srams and then returned to the l2sync_in input of the PC7410 to synchronize l2clkout at the sram with the processor?s internal clock. l2clkout at the sram can be offset for- ward or backward in time by shortening or lengthening the routing of l2sync_out to l2sync_in. see motorola application note an179/d "powerpc backside l2 timing analysis for the pcb design engineer." the minimum l2clk frequency of table 12 is specified by the maximum delay of the internal dll. the variable-tap dll introduces up to a full clock period delay in the l2clkouta, l2clkoutb and l2sync_ou t signals so that the returning l2sync_in signal is phase aligned with the next core clock (divided by the l2 divisor ratio). do not choose a core-to-l2 divisor which results in an l2 frequency below this minimum, or the l2clkout signals provi ded for sram clocking will not be phase aligned with the PC7410 core clock at the srams. the maximum l2clk frequency shown in table 12 is the core frequency divided by one. very few l2 sram designs will be able to operate in th is mode. most designs will select a greater core-to-l2 divisor to provide a longer l2clk period for read and write access to the l2 srams. the maximum l2clk frequency for any application of the PC7410 will be a function of the ac timings of the PC7410, the ac timings for the sram, bus loading and printed circuit board trace length. atmel is similarly limited by system constraints and cannot perform tests of the l2 inter- face on a socketed part on a functional tester at the maximum frequencies of table 12. therefore, functional operation and ac timing information are tested at core-to-l2 divi- sors of 2 or greater. z0 = 50 ? rl = 50 ? ov dd /2 output hreset mode signals sysclk first sample second sample vm vm
24 PC7410 2141d?hirel?02/04 l2 input and output signals are latched or enab led respectively by the internal l2clk (which is sysclk multiplied up to the core frequency and divided down to the l2clk frequency). in other words, the ac timings of table 13 are entirely independent of l2sync_in. in a closed loop system, where l2sync_in is driven through the board trace by l2sync_out, l2sync_in only controls the output phase of l2clkouta and l2clkoutb which are used to latch or enable data at the srams. however, since in a closed loop system l2sync_in is held in phase alignment with the internal l2clk, the signals of table 13 are referenced to this signal rather than the not-externally-visible internal l2clk. during manufacturing test, these times are actually measured relative to sysclk. notes: 1. l2clk outputs are l2clk_outa, l2clk_outb, and l2sync_out pins. the l2clk frequency to core frequency set- tings must be chosen such that the resulting l2clk frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. the maximum l2lc k frequency will be system-dependent. l2clk_outa and l2clk_outb must have equal loading. 2. the nominal duty cycle of the l2clk is 50% measur ed at midpoint voltage. 3. the dll re-lock time is specified in terms of l2clks. the num ber in the table must be multiplied by the period of l2clk to compute the actual time duration in nanoseconds. re-lock timing is guaranteed by design and characterization. 4. the l2cr[l2sl] bit should be set for l2clk frequencies less th an 110 mhz. this adds more delay to each tap of the dll. 5. allowable skew between l2sync_out and l2sync_in. 6. guaranteed by design and not tested. this output jitter number represents the maxi mum delay of one tap forward or one tap back from the current dll tap as the phase comparator seek s to minimize the phase difference between l2sync_in and the internal l2clk. this number must be comprehended in the l2 timing analysis. the input jitter on sysclk affects l2clkout and the l2 address/data/control signals equally and therefore is already comprehended in the ac timing and does not have to be considered in the l2 timing analysis. table 12. l2clk output ac timing specif ications at recommended operat ing conditions (see table 4) symbol parameter 400 mhz 450 mhz 500 mhz unit min max min max min max f l2clk (1)(4) l2clk frequency 133 400 133 400 133 400 mhz t l2clk l2clk cycle time 2.5 7 .5 2.5 7.5 2.5 7.5 ns t chcl /t l2clk (2) l2clk duty cycle 50 50 50 % internal dll-relock time (3) 640 640 640 - l2clk dll capture window (5) 010010010ns t l2cskw l2clkout output-to-output skew (6) -50-50-50ps l2clkout output jitter (6) - 150 - 150 - 150 ps
25 PC7410 2141d?hirel?02/04 figure 12. l2clk_out output timing diagram note: vm = midpoint voltage (l2ov dd /2) t chcl t l2clk t l2cr t l2cf l2 single-ended clock mode l2clk_outa l2clk_outb l2sync_out l2clk_outa l2clk_outb l2sync_out t chcl t l2clk vm vm vm vm vm vm vm vm vm vm vm vm vm vm vm t l2cskw vm l2 differential clock mode
26 PC7410 2141d?hirel?02/04 l2 bus ac specifications table 13 provides the l2 bus interface ac timing specifications for the PC7410 as defined in figure 13 and figure 14 for the loading conditions described in figure 15. notes: 1. rise and fall times for the l2sync_in input are measured from 20% to 80% of l2ov dd . 2. all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input l2sync_in (see figure 13). input timings are measured at the pins. 3. all output specifications are me asured from the midpoint voltage of the rising edge of l2sync_in to the midpoint of the sig- nal in question. the output timings ar e measured at the pins. all output ti mings assume a purely resistive 50 ? load (see figure 15). 4. the outputs are valid for both single-ended and differenti al l2clk modes. for pipelined registered synchronous burst rams, l2cr[14:15] = 00 is recommended. for pipelined late-write synchronous burst srams, l2cr[14:15] = 10 is recommended. figure 13. l2 bus input timing diagram note: vm = midpoint voltage (l2ov dd /2) table 13. l2 bus interface ac timing specifications at v dd = av dd = l2av dd = 1.8v 100mv or 1.5v 50mv ; -55c t j 125c, l2ov dd = 2.5v 100mv or l2ov dd = 1.8v 100mv symbol parameter 400, 450, 500 mhz unit min max t l2cr & t l2cf (1) l2sync_in rise and fall time 1.0 ns t dvl2ch (2) setup times data and parity 1.5 ns t dxl2ch (2) input hold times data and parity 0.0 ns t l2chov (3)(4) valid times all outputs when l2cr[14:15] = 00 all outputs when l2cr[14:15] = 01 all outputs when l2cr[14:15] = 10 all outputs when l2cr[14:15] = 11 2.5 2.5 2.9 3.5 ns t l2chox (3) output hold times all outputs when l2cr[14:15] = 00 all outputs when l2cr[14:15] = 01 all outputs when l2cr[14:15] = 10 all outputs when l2cr[14:15] = 11 0.4 0.8 1.2 1.6 ns t l2choz l2sync_in to high impedance all outputs when l2cr[14:15] = 00 all outputs when l2cr[14:15] = 01 all outputs when l2cr[14:15] = 10 all outputs when l2cr[14:15] = 11 2.0 2.5 3.0 3.5 ns l2sync_in l2 data and data parity inputs t l2cr t l2cf t dvl2ch t dxl2ch vm
27 PC7410 2141d?hirel?02/04 figure 14. l2 bus output timing diagram note: vm = midpoint voltage (l2ov dd /2) figure 15. ac test load for the l2 interface l2sync_in all outputs t l2chov t l2chox vm vm t l2choz l2data bus z0 = 50 ? rl = 50 ? l2ov dd /2 output
28 PC7410 2141d?hirel?02/04 ieee 1149.1 ac timing specifications table 14 provides the ieee 1149.1 (jtag) ac timi ng specifications as defined in figure 16, figure 17, figure 18 and figure 19. notes: 1. all outputs are measured from the midpoint voltage of the falling/rising edge of tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50 ? load (see figure 16). time-of-flight delays must be added for tr ace lengths, vias and co nnectors in the system. 2. trst is an asynchronous level sensitive si gnal. the setup time is for test purposes only. 3. non-jtag signal input timing with respect to tck. 4. non-jtag signal output timing with respect to tck. 5. guaranteed by design and characterization figure 16. alternate ac test load for the jtag interface figure 17. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2) table 14. jtag ac timing specificat ions (independent of sysclk) (1) at recom- mended operating conditions (see table 4) symbol parameter min max unit f tclk tck frequency of operation 0 33.3 mhz t tclk tck cycle time 30 ns t jhjl tck clock pulse width measured at ovdd/2 15 ns t jr & t jf tck rise and fall times 0 2 ns t trst (2) trst assert time 25 ns t dvjh (3) t ivjh input setup times: boundary-scan data tms, tdi 4 0 ns t dxjh (3) t ixjh input hold times: boundary-scan data tms, tdi 20 25 ns t jldv (4) t jlov valid times: boundary-scan data tdo 4 4 20 25 ns t jldz (4)(5) t jloz (5) tck to output high impedance: boundary-scan data tdo 3 3 19 9 ns z0 = 50 ? rl = 50 ? ov dd /2 output t clk t jr t jf t jhjl t tclk vm vm vm
29 PC7410 2141d?hirel?02/04 figure 18. trst timing diagram note: vm = midpoint voltage (ov dd /2) figure 19. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2) figure 20. test access port timing diagram note: vm = midpoint voltage (ov dd /2) trst t trst vm vm tck t jldx vm boundary data inputs boundary data outputs boundary data outputs vm input data valid t d vjh t dxjh t jld v t jldz output data valid output data valid tck t jlox vm tdi, tms tdo tdo vm input data valid t ivjh t ixjh t jlov t jloz output data valid output data valid
30 PC7410 2141d?hirel?02/04 preparation for delivery handling mos devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of static buildup. however, the following handling practices are recommended: devices should be handled on benches with conductive and grounded surfaces. ground test equipment, tools and operator. do not handle devices by the leads. store devices in conduc tive foam or carriers. avoid use of plastic, rubber or silk in mos areas. maintain relative humidity above 50% if practical. for ci-cga packages, use specific tray to take care of the highest height of the package compared with the normal cbga. package mechanical data parameters the package parameters are as provided in the following list. the package type is 25x25 mm, 360-lead cbga, hitce and ci-cga. the following remarks apply to figure 26 and figure 27: dimensions and tolerancing are as per asme y14.5m-1994. all dimensions are in millimeters. top side a1 corner index is a metallized feature with various shapes. bottom side a1 corner is designated with a ball missing from the array. dimension b is the maximum solder ball diameter measured parallel to datum a. d2 and e2 define the area o ccupied by the die an d underfill. actual si ze of this area may be smaller than shown. d3 and e3 are the minimum clearance from the package edge to the chip capacitors. table 15. package parameters parameter package outline 25 mm x 25 mm interconnects 360 (19 x 19 ball array minus one) pitch 1.27 mm (50 mil) minimum module height 2.65 mm (c bga, hitce), 3.65 mm (ci-cga) maximum module height 3.20 mm (cbga) , 3.24 mm (hitce), 4.20 mm (ci-cga) ball or column diameter 0.89 mm (35 mil)
31 PC7410 2141d?hirel?02/04 pin assignment bga360 package figure 21, figure 22, figure 23 and figure 24 show top views of the packages available for the PC7410. note that these drawings are not to scale. figure 21. top view of 360-ball cbga and 360-pin ci-cga packages figure 22. top view of 360-pin cbga and ci-cga packages pin a1 index a b c d e f g h j k l m n p r t 12 3 4 5678 910111213141516 17 18 19 u v w
32 PC7410 2141d?hirel?02/04 figure 23. cross-section of 360-ball cbga and hitce package figure 24. cross-section of 360-column ci-cga package substrate assembly encapsulant view die view die substrate assembly encapsulant table 16. pinout listing for the PC7410, 360-ball cbga and ci-cga packages signal name pin number active i/o i/f select (1) a[0:31] a13, d2, h11, c1, b13, f2, c13, e5, d13, g7, f12, g3, g6, h2, e2, l3, g5, l4, g4, j4, h7 , e1, g2, f3, j7, m3, h3, j2, j6, k3, k2, l2 high i/o bvsel aack n3 low input bvsel abb (12) amon[0] (12) l7 low output bvsel ap[0:3] c4, c5, c6, c7 high i/o bvsel artry l6 low i/o bvsel av dd a8 vdd bg h1 low input bvsel br e7 low output bvsel bvsel (1)(3)(8)(9)(14) w1 high input n/a chk (4)(8)(9) k11 low input bvsel ci c2 low i/o bvsel ckstp_in b8 low input bvsel ckstp_out d7 low output bvsel clk_out e3 high output bvsel dbb (12) dmon[0] (12) k5 low output bvsel dbg k1 low input bvsel
33 PC7410 2141d?hirel?02/04 dh[0:31] w12, w11, v11, t9, w10, u9, u10, m11, m9, p8, w7, p9, w9, r10, w6, v7, v6, u8, v9, t7, u7, r7, u6, w5, u5, w4, p7, v5, v4, w3, u4, r5 high i/o bvsel dl[0:31] m6, p3, n4, n5, r3, m7, t2 , n6, u2, n7, p11, v13, u12, p12, t13, w13, u13, v10, w8, t11, u11, v12, v8, t1, p1, v1, u1, n1, r2, v3, u3, w2 high i/o bvsel dp[0:7] l1, p2, m2, v2, m1, n2, t3, r1 high i/o bvsel drdy (6)(8)(13) k9 low output bvsel dbwo dti[0] d1 low input bvsel dti[1:2] (10)(13) h6, g1 high input bvsel emode (7)(10) a3 low input bvsel gbl b1 low i/o bvsel gnd d10, d14, d16, d4, d6, e12, e8, f4, f6, f10, f14, f16, g9, g11, h5, h8, h10, h12, h15, j9, j11, k4, k6, k8, k10, k12, k14, k16, l9, l11, m5, m8, m10, m12, m15, n9, n11, p4, p6, p10, p14, p16, r8, r1 2, t4, t6, t10, t14, t16 n/a hit (6)(8) b5 low output bvsel hreset b6 low input bvsel int c11 low input bvsel l1_tstclk (2) f8 high input bvsel l2addr[0:16] l17, l18, l19, m19, k18, k1 7, k15, j19, j18, j17, j16, h18, h17, j14, j13, h19, g18 high output l2vsel l2addr[17:18] (8) k19, w19 high output l2vsel l2av dd l13 vdd l2ce p17 low output l2vsel l2clkouta n15 high output l2vsel l2clkoutb l16 high output l2vsel l2data[0:63] u14, r13, w14, w15, v15, u15, w16, v16, w17, v17, u17, w18, v18, u18, v19, u19, t18, t17, r19, r18, r17, r15, p19, p18, p13, n14, n13, n19, n17, m17, m13, m18, h13, g19, g16, g15, g14, g13, f19, f18, f 13, e19, e18, e17, e15, d19, d18, d17, c18, c17, b19, b18, b17, a18, a17, a16, b16, c16, a14, a 15, c15, b14, c14, e13 high i/o l2vsel l2dp[0:7] v14, u16, t 19, n18, h14, f17, c19, b15 high i/o l2vsel l2ov dd (11) d15, e14, e16, h16, j15, l15 , m16, k13, p15, r14, r16, t15, f15 n/a l2sync_in l14 high input l2vsel l2sync_out m14 high output l2vsel l2_tstclk (2) f7 high input bvsel l2vsel (1)(3)(8)(9)(14) a19 high input n/a table 16. pinout listing for the PC7410, 360-ball cbga and ci-cga packages (continued) signal name pin number active i/o i/f select (1)
34 PC7410 2141d?hirel?02/04 notes: 1. ov dd supplies power to the processor bus, jtag and all control signals except the l2 cache controls (l2ce , l2we , and l2zz ); l2ov dd supplies power to the l2 cache interface (l2a ddr[0:18], l2aspare, l2dat a[0:63], l2dp[ 0:7] and l2sync_out) and the l2 control signals and v dd supplies power to the processor core and the pll and dll (after filtering to become av dd and l2av dd respectively). these columns serve as a re ference for the nominal voltage supported on a given signal as selected by the bvsel/l2vsel pin configurati ons of table 3 and the voltage supplied. for actual recom- mended value of v in or supply voltages, see table 4. 2. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 3. to allow for future i/o voltage changes, provide the option to connect bvsel and l2vsel independently to either ov dd (selects 2.5v), gnd (sel ects 1.8v), or to hreset (selects 2.5v). the PC7410 both the 60x processor bus and the l2 bus only support the 1.8 and 2.5 options (see table 3). the defaul t selection if bvsel and/or l2vsel is left unconnected is 2.5v 4. connect to hreset to trigger post power-on-reset (por) internal memory test. l2we n16 low output l2vsel l2zz g17 high output l2vsel lssd_mode (2) f9 low input bvsel mcp b11 low input bvsel ov dd d5, d8, d12, e4, e6, e9, e11, f5, h4, j5, l5, m4, p5, r4, r6, r9, r11, t5, t8, t12 n/a pll_cfg[0:3] a4, a5, a6, a7 high input bvsel qack b2 low input bvsel qreq j3 low output bvsel rsrv d3 low output bvsel shd0 (8) b3 low i/o bvsel shd1 (5)(8) b4 low i/o bvsel smi a12 low input bvsel sreset e10 low input bvsel sysclk h9 input bvsel ta f1 low input bvsel tben a2 high input bvsel tbst a11 low output bvsel tck b10 high input bvsel tdi (9) b7 high input bvsel tdo d9 high output bvsel tea j1 low input bvsel tms (9) c8 high input bvsel trst (9)(14) a10 low input bvsel ts k7 low i/o bvsel tsiz[0:2] a9, b9 , c9 high output bvsel tt[0:4] c10, d11, b12, c12, f11 high i/o bvsel wt c3 low i/o bvsel v dd g8, g10, g12, j8, j10, j12, l8, l10, l12, n8, n10, n12 n/a table 16. pinout listing for the PC7410, 360-ball cbga and ci-cga packages (continued) signal name pin number active i/o i/f select (1)
35 PC7410 2141d?hirel?02/04 5. ignored in 60x bus mode. 6. unused output in 60x bus mode. 7. deasserted (pulled high) at hreset for 60x bus mode. 8. uses one of 9 existing no-connects in pc750?s 360-ball bga package. 9. internal pull-up on die. 10. reuses pc750?s drtry , dbdis and tlbisync pins (dti1, dti2 and emode respectively). 11. the voltdet pin position on the pc750 360-ball cbga package is now an l2ov dd pin on the PC7410 packages. 12. output only for PC7410, was i/o for pc750. 13. enhanced mode only. 14. to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less than 250 ? should be used.
36 PC7410 2141d?hirel?02/04 figure 25. mechanical dimensions and bottom surface nomenclature of the 360-ball cbga package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metallized feature with various sh apes. bottom side a1 corner is designated with a ball missing from the array pack a ge caps value f voltage reference c1-1 0.01 l2ov dd c1-2 gnd c2-1 0.01 l2o v dd c2-2 gnd c3-1 0.01 v dd c3-2 gnd c4-1 0.01 ov dd c4-2 gnd c5-1 0.01 ov dd c5-2 gnd c6-1 0.01 v dd c6-2 gnd millimeters dim min max a 2,72 3,2 a1 0,8 1 a2 1,1 1,3 a3 0,6 a4 0,82 0,9 b 0,82 0,93 d 25 bsc d2 10 typ d3 6,32 e1,27 bsc e 25 bsc e2 12,6 typ e3 8, 26 j1 0, 89 bsc j2 3,2 bsc j3 0, 68 bsc k1 6,56 k2 8,13 l1 8,61 l2 7,04 b c 360x e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b 171819 u w v d2 d3 d c6-2 c6-1 e2 e b e3 0.2 2x 0.2 2x a c1-1 c1-2 12x j2 l2 l1 c5-1 c5-2 c2-2 c2-1 c4-1 c3-1 c3-2 c4-2 12x j1 12x j3 k2 k1 a1 corner 0.15 a 0.25 a 0.35 a c a3 a2 a4 a1 a
37 PC7410 2141d?hirel?02/04 figure 26. mechanical dimensions and bottom surface nomenclature of the 360-ball hitce package notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 2. dimensions in millimeters 3. top side a1 corner index is a metallized feature with various sh apes. bottom side a1 corner is designated with a ball missing from the array pack a ge caps value f voltage reference c1-1 0.01 l2ov dd c1-2 gnd c2-1 0.01 l2o v dd c2-2 gnd c3-1 0.01 v dd c3-2 gnd c4-1 0.01 ov dd c4-2 gnd c5-1 0.01 ov dd c5-2 gnd c6-1 0.01 v dd c6-2 gnd millimeters dim min max a 2,72 3,2 a1 0,8 1 a2 1,1 1,3 a3 0,6 a4 0,82 0,9 b 0,82 0,93 d 25 bsc d2 10 typ d3 6,32 e1,27 bsc e 25 bsc e2 12,6 typ e3 8, 26 j1 0, 89 bsc j2 3,2 bsc j3 0, 68 bsc k1 6,56 k2 8,13 l1 8,61 l2 7,04 b c 360x e 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t a 0.3 c 0.15 b 171819 u w v d2 d3 d c6-2 c6-1 e2 e b e3 0.2 2x 0.2 2x a c1-1 c1-2 12x j2 l2 l1 c5-1 c5-2 c2-2 c2-1 c4-1 c3-1 c3-2 c4-2 12x j1 12x j3 k2 k1 a1 corner 0.15 a 0.25 a 0.35 a c a3 a2 a4 a1 a
38 PC7410 2141d?hirel?02/04 figure 27. mechanical dimensions and bottom surface nome nclature of the 360-column ci-cga package parameter min max parameter min max a 3.4 4.20 d3 2.75 ? a1 1.545 1.695 d4 6.32 a2 1.10 1.30 e 25.00 basic a3 ? 0.6 e1 22.86 basic a4 0.82 0.9 e2 ? 15 b 0.820.93e33.00? d 25.00 basic e4 8.26 d1 22.86 basic g 1.27 basic d2 ? 13 a a1 a2 a 0.15 a f t 360x g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t e 0.3 t 0.15 b 171819 u w v k k d pin a1 e d4 0.2 2x b e2 top view index d3 e3 0.2 2x a3 a4 d1 e1 c d2 e4 0.15 2x 360x 0.35 a gnd : c1.2 c2.2 c3.2 c4.2 c5.2 c6.2 c1.1, c2.1 : l2ovdd c3.1, c6.1 : ovdd c4.1, c5.1 : ovdd c6 c1 c2 c3 c4 c5 2 1 12 12 1 2 2 1 2 1
39 PC7410 2141d?hirel?02/04 clock selection the PC7410?s pll is configured by the pll_cfg[0:3] signals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the PC7410 is shown in table 17 for example frequencies. in this example, shaded cells re present settings that, for a given sysclk frequency, result in core and/or vco frequencies that do not comply with the minimum and maximum core frequencies listed in table 11. notes: 1. pll_cfg[0:3] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference onl y. some pll configurations may select bus, core, or vco frequencies which are not useful, not supp orted, or not tested for by the PC7410; see ?clock ac specifications? on page 20 for valid sysclk, core, and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use and third- party emulator tool development only. note: the ac timing specifications given in th is document do not apply in pll-bypass mode. 4. in pll-off mode, no clocking occurs insi de the PC7410 re gardless of the sysclk input. 5. pll-off mode should not be used during chip power-up sequencing. table 17. PC7410 microprocessor pll configuration (1)(2)(3)(4)(5) pll_cfg [0:3] example bus-to-core frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to- vco multiplier bus 33.3 mhz bus 50 mhz bus 66.6 mhz bus 75 mhz bus 83.3 mhz bus 100 mhz bus 133 mhz 0100 2x 2x 0110 2.5x 2x 1000 3x 2x 400 (800) 1110 3.5x 2x 350 (700) 465 (930) 1010 4x 2x 400 (800) 0111 4.5x 2x 375 (750) 450 (900) 1011 5x 2x 375 (750) 416 (833) 500 (1000) 1001 5.5x 2x 366 (733) 412 (825) 458 (916) 1101 6x 2x 400 (800) 450 (900) 500 (1000) 0101 6.5x 2x 433 (866) 488 (967) 0010 7x 2x 350 (700) 466 (933) 0001 7.5x 2x 375 (750) 500 (1000) 1100 8x 2x 400 (800) 0000 9x 2x 450 (900) 0011 pll off/bypass pll off, sysclk clocks core circuitry directly, 1x bus-to-core implied 1111 pll off pll off, no core clocking occurs
40 PC7410 2141d?hirel?02/04 the PC7410 generates the clock for the external l2 synchronous data srams by divid- ing the core clock frequency of the PC7410. the divided-down clock is then phase- adjusted by an on-chip delay -lock-loop (dll) circuit and should be routed from the PC74107410 to the external rams. a separa te clock output, l2sync_out is sent out half the distance to the srams and then returned as an input to the dll on pin l2sync_in so that the rising-edge of the cl ock as seen at the external rams can be aligned to the clocking of the internal latches in the l2 bus interface. the core-to-l2 frequency divisor for the l2 pll is selected through the l2clk bits of the l2cr register. generally, the divisor must be chosen according to the frequency supported by the external rams, the frequency of the PC7410 core, and the phase adjustment range that the l2 dll supports. table 18 shows various example l2 clock frequencies that can be obtained for a given set of core frequencies. the minimum l2 frequency target is 133 mhz. sample core-to-l2 frequencies for the PC7410 is shown in table 18. in this example, shaded cells repr esent settings that, for a given core fre- quency, result in l2 frequencies that do not comply with the minimum and maximum l2 frequencies listed in table 14. note: the core and l2 frequencies are for reference only. some examples may represent core or l2 frequencies which are not useful, not supported or not tested for by the PC7410; see ?l2 clock ac specifications? on page 23 for valid l2clk frequencies. the l2cr[l2sl] bit should be set for l2clk frequencies less than 150 mhz. system design information pll and dll power supply filtering the av dd and l2av dd power signals are provided on the PC7410 to supply power to the pll and dll, respectively. on systems that use the PC7410 cbga device, the l2av dd filter should implement the circuit shown in figure 28. the av dd filter on the PC7410 cbga device should imple- ment the circuit shown in figure 29. on systems that use the PC7410 hitce device, the av dd and l2av dd input signals should both implement the circuit shown in figure 28. the circuit shown below should be pl aced as close as possible to the av dd pin to mini- mize noise coupled from nearby circuits. a separate circuit should be placed as close as possible to the l2av dd pin. it is often possible to route directly from the capacitors to the av dd pin, which is on the periphery of the 360 cbga footprint, without the inductance of vias. the l2av dd pin may be more difficult to route, but is proportionately less critical. table 18. sample core-to-l2 frequencies core frequency in mhz11.522.533.54 350 350 233 175 140 ? ? ? 366 366 244 183 147 ? ? ? 400 400 266 200 160 133 ? ? 433 ? 288 216 173 144 ? ? 450 ? 300 225 180 150 ? ? 466 ? 311 233 186 155 133 ? 500 ? 333 250 200 166 143 ?
41 PC7410 2141d?hirel?02/04 it is the recommendation of motorola, that systems that implement the av dd filter shown in figure 29 design in the pads for the removed capacitors (shown in figure 28), to pro- vide for the possible reintroduction of the filter in figure 28. this would be necessary in case there is a planned transition to the hcte package of the PC7410. figure 28. pll power supply filter circuit #1 figure 29. pll power supply filter circuit #2 power supply voltage sequency the notes in table 2 contain cautions about the sequencing of the external bus voltages and core voltage of the PC7410 (when they are different). these cautions are necessary for the long term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes will be forward-bias ed and excessive current can flow through these diodes. if the system power suppl y design does not control the voltage sequenc- ing, one or both of the circuits of figure 30 can be added to meet these requirements. the mur420 schottky diodes of figure 30 control the maximum potential difference between the external bus and core power supplies on power-up and the 1n5820 diodes regulate the maximum potential difference on power-down. figure 30. example voltage sequencing circuits v dd 10 ? 2.2 f 2.2 f gnd av dd (or l2av dd ) low esl surface mount capacitor v dd av d d 51 ? gnd capacitor pad sites mur420 mur420 1n5820 1n5820 1.8v 2.5v
42 PC7410 2141d?hirel?02/04 decoupling recommendations due to the PC7410?s dynamic power management feature, large address and data buses and high operating frequencies, the PC7410 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the PC7410 system and the PC7410 itself requires a clean, tightly regulated source of power. there- fore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , ov dd , and l2ov dd pin of the PC7410. it is also recommended that these decoupling capacitors receive their power from separate v dd , (l2)ov dd , and gnd power planes in the pc b, utilizing short traces to minimize inductance. these capacitors should have a value of 0.01 f or 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993) and contrary to previous rec- ommendations for decoupling powerpc micropro cessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , l2ov dd , and ov dd planes to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors are 100 - 330 f (avx tps tantalum or sanyo oscon). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , l2ov dd , and gnd pins of the PC7410. see ?l2 clock ac specifications? on page 23 for a discussion of the l2sync_out and l2sync_in signals. output buffer dc impedance the PC7410 60x and l2 i/o drivers are charac terized over process, voltage and tem- perature. to measure z 0 , an external resistor is connected from the chip pad to ov dd or gnd. then the value of each resistor is varied until the pad voltage is ov dd /2 (see fig- ure 31). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held low, sw2 is closed (sw1 is open), and r n is trimmed until the voltage at the pad equals ov dd /2. r n then becomes the resistance of the pull-down devices. when data is held hi gh, sw1 is closed (sw2 is open), and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then z 0 = (r p + r n )/2.
43 PC7410 2141d?hirel?02/04 figure 31. driver impedance measurement table 19 summarizes the signal impedance results. the impedance increases with junc- tion temperature and is relatively unaffected by bus voltage. pull-up resistor requirements the PC7410 requires pull-up resistors (1 k ? ?5 k ? ) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7410 or other bus masters. these pins are: ts , artry , shdo , shd1 . four test pins also require pull-up resistors (100 ? ?1 k ? ). these pins are chk , l1_tstclk, l2_tstclk, and lssd_mode . these signals are for factory use only and must be pulled up to ov dd for normal machine operation. if pull-down resistors are used to configure bvsel or l2vsel, the resistors should be less than 250 ?. (see table 12). because pll_cfg[0:3] must remain stable during nor- mal operation, strong pull-up and pull-down resistors (1 k ? or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. in addition, ckstp_out is an open-drain style output that requires a pull-up resistor (1 k ? ?5 k ? ) if it is used by the system. the ckstp_in signal should likewise be pulled up through a pull-up resistor (1 k ? ?5 k ? ) to prevent erroneous assertions of this signal. table 19. impedance characteristics with v dd = 1.8v, ov dd = 1.8v or 2.5v, t j = -55 c to 125 c impedance processor bus l2 bus symbol unit r n 41.5 - 54.3 42.7 - 54.1 z 0 ohms r p 37.3 - 55.3 39.3 - 50 z 0 ohms ov dd ognd sw2 sw1 rn rp pad data
44 PC7410 2141d?hirel?02/04 during inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. since the PC7410 mu st continually monitor these signals for snooping, this float condition may cause exce ssive power draw by the input receivers on the PC7410 or by other receivers in the system. these signals can be pulled up through weak (10 k ? ) pull-up resistors by the system, address bus driven mode can be enabled (see the PC7410 risc microporcessor family users? manual for more information on this mode), or these signals may be otherwis e driven by the system during inactive peri- ods of the bus to avoid this additional power draw. the snooped address and transfer attribute inputs are: a[0:31], ap[0:3], tt[0:4], ci , wt , and gbl . in systems where gbl is not connected and other devices may be asserting ts for a snoopable transaction while not driving gbl to the processor, we recommend that a strong (1 k ? ) pull-up resistor be used on gbl . note that the PC7410 will only snoop transactions when gbl is asserted. the data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. other data bus receivers in the system, howeve r, may require pull-ups, or that those signals be other- wise driven by the system during inactive pe riods by the system. the data bus signals are: dh[0:31], dl[0:31], and dp[0:7]. if address or data parity is not used by the system, and the respective parity checking is disabled through hid0, the input receivers fo r those pins are disa bled, and those pins do not require pull-up resistors and should be left unconnected by the system. if parity checking is disabled through hid0, and par ity generation is not required by the PC7410 (note that the PC7410 always generates parity), then all parity pins may be left uncon- nected by the system. the l2 interface does not normally require pull-up resistors.
45 PC7410 2141d?hirel?02/04 jtag configuration signals boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that imple- ment the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset perfor- mance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to i ndependently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures , or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 32 allows the cop port to independently assert hreset or trst , while ensuring that t he target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset through a 0 ? isolation resistor so that it is as serted when the system reset signal (hreset ) is asserted ensuring that the jtag scan chain is initialized during power-on. while motor- ola recommends that the cop header be designed into the system as shown in figure 32, if this is not possible, the isolation resistor will allow future access to trst in the case where a jtag interface may need to be wired onto the system in debug situations. the cop header shown in figure 32 adds many benefits ? breakpoints, watchpoints, register and memory examination/modifi cation, and other standard debugger features are possible through this interface ? and ca n be as inexpensive as an unpopulated footprint for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key. there is no standardized way to number the cop header shown in figure 32; conse- quently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to- bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal plac ement recommended in figure 32 is com- mon to all known emulators. the qack signal shown in figure 32 is usually connected to the pci bridge chip in a system and is an input to the PC7410 informing it that it can go into the quiescent state. under normal operation this occurs during a low-power mode selection. in order for cop to work, the PC7410 must see this signal asserted (pulled down). while shown on the cop header, not all emulator products drive this signal. if the product does not, a pull-down resistor can be populated to assert this signal. additionally, some emulator products implement open-drain ty pe outputs and can only drive qack asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. note that the pull-up and pull-down resistors on the qack signal are mutually exclusive and it is never necessary to populate both in a system. to preserve correct power-down operation, qack should be merged via logic so that it also can be driven by the pci bridge.
46 PC7410 2141d?hirel?02/04 figure 32. cop connector diagram notes: 1. run/stop , normally found on pin 5 of the co p header, is not implemented on the PC7410. connect pin 5 of the cop header to ov dd with a 10 k ? pull-up resistor. 2. key location; pin 14 is not phys ically present on the cop header. 3. component not populated. populate only if debug tool does not drive qack . 4. populate only if debug tool uses an open -drain type output and does not actively deassert qack . 5. if the jtag interface is implemented, connect hreset from the target source to trst from the cop header though an and gate to trst of the part. if the jtag interface is not implemented, connect hreset from the target source to trst of the part through a 0 ? isolation resistor . 6. the cop port and target board should be able to independently assert hreset and trst to the processor in order to fully control the processor as shown above. hreset hreset hreset 13 sreset sreset sreset nc nc 11 vdd_sense 6 5 (1) 15 2 k ? 10 k ? 10 k ? 10 k ? ov dd ov dd ov dd ov dd chkstp_in chkstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 cop header 14 (2) key qack ov dd ov dd 10 k ? ov dd trst 10 k ? ov dd 10 k ? 10 k ? qack qack chkstp_out chkstp_out 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin cop connector physical pin out 10 k ? (4) ov dd 1 2 k ? (3) 0 ? (5) from target board sources (if any) (6) (6)
47 PC7410 2141d?hirel?02/04 boundary scan testing is enabled through the jtag interface signals. (bsdl descrip- tions of the PC7410 are available on the internet at www.mot.com/powerpc/teksupport.) the trst signal is optional in the ieee 1149.1 specification but is provided on all powerp c implementations. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on rese t performance will be obtained if the trst signal is asserted dur- ing power-on reset. since the jtag interface is also used for accessing the common on-chip processor (cop) function of powerpc processors, simply tying trst to hreset is not practical. the common on-chip processor (cop) function of powerpc processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface con- nects primarily through the jtag port of the processor with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the proce ssor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in fi gure 32 allows the cop to independently assert hreset or trst , while ensuring that the target can drive hreset as well. the pull-down resis- tor on trst ensures that the jtag scan chain is initialized during power-on if a jtag interface cable is not attached; if it is attached, it is responsible for driving trst when needed. table 20. cop pin definitions pins signal connection special notes 1tdo tdo 2qack qack add 2k pull-down to ground. must be merged with on-board qack , if any. 3tdi tdi 4trst trst add 2k pull-down to ground. must be merged with on-board trst if any. see figure 32. 5 run/stop no connect used on 604e; leave no-connect for all other processors. 6 vdd_sense vdd add 2k pull-up to ov dd (for short circuit limiting protection only). 7tck tck 8 ckstp_in ckstp_in optional. add 10k pull-up to ov dd . used on several emulator products. useful for checkstopping the processor from a logic analyzer of other external trigger. 9tms tms 10 n/a 11 sreset sreset merge with on-board sreset , if any. 12 n/a 13 hreset hreset merge with on-board hreset. 14 n/a key location; pin should be removed. 15 ckstp_out ckstp_out add 10k pull-up to ov dd . 16 ground digital ground
48 PC7410 2141d?hirel?02/04 the cop header shown in figure 32 adds many benefits ? breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface ? and can be as inexpensive as an unpopulated foot- print for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025? square-post 0.100? centered header assembly (often called a ?berg? header). the connector typically has pin 14 removed as a connector key, as shown in figure 32.
49 PC7410 2141d?hirel?02/04 definitions datasheet status description life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can r easonably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify atmel for any damages resulting from such improper use or sale. table 21. datasheet status datasheet status validity objective specification this datasheet contains target and goal specifications for discussion with customer and application validation. before design phase target specification this datas heet contains target or goal specifications for product development. valid during the design phase preliminary specification -site this datasheet contai ns preliminary data. additional data may be published later; could include simulation results. valid before characterization phase preliminary specification -site this datasheet also contains characterization results. valid before the industrialization phase product specification this data sheet contains final product specification. valid for production purposes limiting values limiting values given are in accordance with the absolute maxi mum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sect ions of the specification is not implied. exposure to limitin g values for extended periods may affect device reliability. application information where application information is given, it is advis ory and does not form part of the specification.
50 PC7410 2141d?hirel?02/04 ordering information note: 1. for availability of the different versions, contact your local atmel sales office. document revision history table 22 provides a revision histor y for this hardware specification. pc 7410 v gs u l x prefix type package (1) g: cbga gs: ci-cbga gh: hitce screening level (1) u: upscreening revision level (1) rev. e application modifier (1) l: 1.8v 100 mv n: 1.5v 50 mv (400 mhz only) temperature range: t j (1) v: -40?c, +110?c m: -55?c, +125?c prototype (x) max internal processor speed (1) 400 mhz 450 mhz 500 mhz (tbc) 400 table 22. document revision history rev. no substantive change(s) d public release, includes rev 1.1 changes. section ? added package capacitor values. section "thermal management assistant"? deleted section ?pull-up resistor requirements? on page 43 ? ad ded recommendation that strong pull-up/down resistors be used on the pll_cfg[0:3] signals. table 11 on page 21? removed mode input setup and hold times. these inputs adhere to the general input setup and hold specifications. figure 11 on page 23 ? revised mode input diagram to show sample points around hreset negation. figure 32 on page 46 ? added note 6 to emphasize that cop emulator and target board need to be able to drive hreset and trst independently to the cpu. section ?pll and dll power supply filtering? on page 40 ? revised section for hcte package. added text and figure for av dd filter for the cbga package. section ?pull-up resistor requirements? on page 43 ? removed aack , tea , and ts from control signals requiring pull-ups. removed tbst from snooped transfer attribute list. tbst is an output and is not snooped.
i PC7410 2141d?hirel?02/04 table of contents features .............. .............. .............. ............... .............. .............. ...........1 description .......... .............. .............. ............... .............. .............. .......... 1 screening ........... .............. .............. ............... .............. .............. ...........2 block diagram ........... ................. ................ ................. .............. ...........3 general parameters............. .............. .............. .............. .............. ........ 4 features .............. .............. .............. ............... .............. .............. ...........4 signal description ............... .............. .............. .............. .............. ........ 8 detailed specification ........ .............. .............. .............. .............. .........9 scope ................ ................ .............. ............... .............. .............. ...........9 applicable documents ......... ................ ................. ................ ..............9 requirements ................... .............. ............... .............. .............. ...........9 general ................................................................................................................. 9 design and construction ...................................................................................... 9 terminal connections ................................................................................... 9 absolute maximum ratings .................................................................................. 9 recommended operating conditions ................................................................. 11 thermal characteristics ...................................................................................... 12 package characteristics ............................................................................. 12 internal package conduction resistance ................................................... 13 thermal management information .............................................................. 13 adhesives and thermal interface materials ................................................ 14 power consideration .......................................................................................... 17 power management..................................................................................... 17 power dissipation ....................................................................................... 18 electrical characteristics.... ................ ................. ................ ............. 19 static characteristics .......................................................................................... 19 dynamic characteristics ..................................................................................... 20 clock ac specifications .............................................................................. 20 processor bus ac specifications ............................................................... 21 l2 clock ac specifications ......................................................................... 23 l2 bus ac specifications ............................................................................26 ieee 1149.1 ac timing specifications....................................................... 28 preparation for delivery ...... ................ ................. ................ ............. 30 handling ........... .............. .............. .............. .............. .............. ............30
ii PC7410 [preliminary] 2141d?hirel?02/04 package mechanical data .. ................ ................. ................ ..............30 parameters .........................................................................................................30 pin assignment.......... ................. ................ .............. .............. ........... 31 bga360 package ............................................................................................... 31 clock selection ................ .............. ............... .............. .............. .........39 system design information ... ................. ................ .............. ............40 pll and dll power supply filtering.................................................................. 40 power supply voltage sequency ....................................................................... 41 decoupling recommendations........................................................................... 42 connection recommendations............................................................................42 output buffer dc impedance ............................................................................. 42 pull-up resistor requirements ........................................................................... 43 jtag configuration signals ............................................................................... 45 definitions ............. ................ ................ ................. ................ ............49 datasheet status description ............................................................................. 49 life support applications .................................................................................... 49 ordering information ............ ................ ................. ................ ............50 document revision history ................. ................. ................ ............50
iii PC7410 2141d?hirel?02/04
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